Split-gate flash technology has been widely employed in medium-low density applications. Conventional split-gate flash memory structures are designed, however, to share the same channel for read, erase, and program (or write) operations, posing severe reliability issues such as data retention and cell endurance. Efforts have been made to enhance data retention and improve endurance characteristics. For example, the structure illustrated in FIG. 1A, including a source region 101, drain regions 103 and 105, trench dielectric 107, channel regions 109 and 111, a floating gate 113, and a control gate 115, utilizes separate channel regions 109 and 111 for reading and programming. As shown in FIGS. 1B and 1C, a read operation employs the left transistor, while a program operation employs the right transistor. Consequently, the structure is less prone to deterioration because no programming stress is applied to the tunneling oxide layer with respect to the channel region designated for reading and, hence, offers better data retention and endurance, as compared with conventional structures.
This approach has proven problematic in several respects. For example, as shown in FIG. 1D, erase operations employ both transistors. As a result, erase and read operations are performed on the same channel, subjecting the reading-designated channel region to erase-induced degradation. The write-designated channel may also experience gate disturbance during read operations, causing undesired data leakage due to stress-induced leakage current (SILC). Additionally, the structure illustrated in FIG. 1A produces a low gate coupling ratio (e.g., CFG/CTOT) during programming (e.g., due to dual channels resulting in a rise in CTOT), indicating decreased program efficiency.
A need therefore exists for flash memory devices exhibiting enhanced data retention and cell endurance, and for enabling methodology.